1. Field
This disclosure relates generally to electrical protection, and more particularly to electrical protection for an integrated circuit.
2. Related Art
An integrated circuit (IC) may be subject to a high voltage event that may overstress the integrated circuit and that can be destructive. An electrostatic discharge (ESD) event is such an overstress event that can be destructive in the manufacturing process, during assembly and testing, or in the system application. Some on-chip ESD protection networks use an active MOSFET (metal oxide semiconductor field-effect transistor) rail clamp protection scheme with large ESD diodes between the input/output (I/O) pads and the power supply rails. This approach has been effective but the currents involved can be quite large so the MOSFET must accordingly be large which is accomplished using many transistors in parallel. One of the mechanisms that is very useful in providing the protection is that an inherent bipolar device, which may be called a bipolar junction transistor (BJT), becomes functional by a mechanism commonly referenced as snap-back. This may occur due to a large voltage between the drain and the source and a change in the potential in the body region that causes the source-body junction diode of the MOSFET to turn on. The potential change in the body region can, for example, be due to drain-body junction leakage current causing a voltage drop along the resistive path from the body region of the MOSFET to the body contact. Once the source-body diode is turned on, current starts flowing between the drain and the source due to the inherent BJT device with the drain as the collector. The large collector current can cause impact ionization current adding to the already flowing drain-body junction leakage current, further turning on the bipolar device. This may ultimately result in the snap-back, which is non-destructive if the high current is for a very short duration. The snap-back results in a significant increase in the current that is provided between the source and drain because much of the current being carried is down in the body region well below the MOSFET channel. Thus, the snap-back is relied upon for providing the needed protection when there is an ESD event. One of the problems is that the triggering of the snap-back is not always uniform so that many of the transistors of the total number of transistors that are in parallel do not actually experience the snap-back which results in a degradation in performance in properly discharging the ESD event. The result is the transistor needs to be bigger than otherwise would be needed if all of the inherent BJTs were ensured of reaching the snap-back condition.
Accordingly there is a need to provide further improvement in achieving snap-back in inherent BJTs in providing protection for temporary high voltage events such as ESD events.